CMOS circuit latches relays

Control applications often require that you set a relay latch in position until you need it to change state. Latching relays accomplish that task. When you send them a pulse, they either remain in the current state or change states, depending on the polarity of the pulse and the current state of the relay. The circuit in Figure 1 switches the state of a DPDT (double-pole/double-throw) latching relay based on a pulse. It comprises a momentary-switch-to-step-voltage-signal generator, a differential-pulse converter, a relay driver, and a relay coil.

A momentary switch produces a step-voltage signal that drives the circuit. The circuit uses a simple pulldown switching action (push-on/release-off), such as the one comprising R_S, C_S, and S₂, or a flip-flop latching action (pushon/ push-off), such as the one comprising IC_1A, IC_1B, R₁, R₂, C₁, and S₁. In the simple pulldown case, you can also add a debounce circuit. The pushbutton switches let you test the circuit before connecting it to another input source.

The differential-pulse converter comprises IC_1C, IC_1D, IC_1E, and IC_1F. The last two stages of the CD4069 hex inverter are self-biased in linear mode around V_DD/2, where V_DD is the drain-to-drain voltage and corresponds to Pin 14 of IC₁. The circuit takes a rise or a fall at IC_1C and converts it to opposing pulses of equal length at the outputs of IC_1E and IC_1F. The order of the pulses is synchronous with the edge direction at the input of IC_1C.

The output-driver stage buffers the voltage outputs of IC_1E and IC_1F to drive the relay coil. The op amps provide differential current dumping through the load without incurring substantial waste in idle mode. An LED-indicator circuit comprising R₄ and D₁ shows the orientation of the relay switch.

Assuming that the circuit powers up with C₁ uncharged, IC_1A and IC_1B always start off in a state in which R₁ sees V_DD on both sides. All inverter stages operate in digital mode except for IC_1E and IC_1F.

When you apply power to the circuit, these two stages self-bias around V_DD/2 and operate in linear mode. The op amps, wired as followers, also bias their outputs near V_DD/2. That action leaves the relay coil with a negligible offset/error voltage thanks to the matching of the devices in the hex-inverter IC and the op amps’ high open-loop gain.

Stages IC_1E and IC_1F ac-couple through capacitors C₅ and C₃, respectively. The capacitors produce an impulse at the inputs of IC_1E and IC_1F from the step outputs of IC_1C and IC_1D. Lossy integrators IC_1E and IC_1F lengthen the inverted pulses at the outputs. Following these events, the outputs of IC_1E and IC_1F gradually return to their equilibrium state, which helps prevent a bucking field from forming in the relay coil and toggling back. Figure 2 shows the shape and timing of the pulses.

R₃/C₃ and R₄/C₄ establish time constants, which roughly set the total length of these pulse tails at 500 msec. This time is more than enough to satisfy the relay coil’s hold requirements, which, for the Panasonic TQ2-L-5V, are 3 msec or less. If the relay coil at first finds itself in an asynchronous position, it can reorient itself after a single push of the switch if necessary.

Dropping IC₁’s V_DD through series-supply resistor R₅ limits the idling currents in linear-biased stages IC_1E and IC_1F. This resistor represents a compromise between the power these two stages dissipate and the available voltage swing to toggle the relay through the op amps.

The circuit operates from a 9V source, and, with the component values in Figure 1, IC₁’s V_DD lies at approximately 5.5V. The overall current draw between toggles is approximately 8 mA.